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| (R) STKM2000 SERIES 2 /2 POLY/2 METAL BiCMOS MIXED ANALOG-DIGITAL STANDARD CELLS s s s s s s s s ADVANCED BICMOS 2 /2 POLY/ 2 METAL PROCESS TWIN TUB PROCESS HIGH LATCH-UP IMMUNITY POWER SUPPLY : MAXIMUM RATING : -0.5V TO 12V OPERATING CONDITIONS : 3V TO 10V MIXED ANALOG - DIGITAL LIBRARY : ANALOG BIPOLAR LIBRARY ANALOG CMOS LIBRARY ANALOG BICMOS LIBRARY DIGITAL CMOS LIBRARY HIGH PROCESS PERFORMANCES: TRANSITION FREQUENCY, NPN = 6 GHz VERTICAL PNP = 2, 5 GHz DIGITAL CMOS OPERATING FREQUENCY : UP TO 30 MHz CAD SOFTWARE SUPPORT: FULLY INTEGRATED A.D.S. (ANALOG DESIGN SYSTEM) WITH ANALOG BLOCK GENERATORS, SWITCHED CAPACITOR FILTER COMPILER; DIGITAL FUNCTIONS GENERATOR, RAM, ROM, PLA GENERATORS AVAILABILITY OF EEPROM DEVICES, ZENER DIODE, SCHOTTKY DIODE s s OPERATING TEMPERATURE RANGE: COMMERCIAL: 0 TO 70oC INDUSTRIAL: -40 TO 85oC MILITARY: -55 TO 125oC PACKAGE OPTIONS: DIL: PLASTIC OR CERAMIC SMD: SO, PLCC, QFP WAFER OR DIE ASIC PRODUCTS DESCRIPTION With the STKM2000 series, SGS-THOMSON Microelectronics introduces the "state of the art" product for analog signal processing, chain from sensor to actuator. The introduction of new concepts (cells library and CAD) opens the design of analog functions and mixed analog and digital circuits with a safe and powerful approach. This new ASIC approach is the combination of innovative : q q q q q BICMOS process Mixed libraries (ANALOG + DIGITAL) Generators and compilers "User friendly" CAD system Customer interface Figure 1 : The STKM2000 Series, a complete system solution SENSOR ~ A A ACTUATOR A/D CONVERTER ~ DSP D/A CONVERTER A 500 mA max. ~ BIP : GB = 100MHz MOS : GB = 10MHz f C(MAX) = 150kHz f MAX = 30MHz 12 Bits +1/2 Bit 15 s 12 Bits +1/2 Bit 15 s November 1989 1/10 STKM2000 SERIES STKM2000 ARCHITECTURE Technology T h e ST KM 20 0 0 Se r ie s de vel ope d by SGS-THOMSON Microelectronics uses an advanced BICMOS silicon gate process with dual polysilicon layers and dual metal layers. This process is optimized to achieve high performance in digital CMOS applications. Depending on the operating supply voltage (10V, or 5V), the CMOS process behaves as an N-WELL technology (respectively with 2 gate length or 1.8 gate length) with operating speeds up to 30MHz. Thanks to the two metal layers, the digital part of the circuit can reach high gate density with low parasitic capacitances. For analog functions, the STKM2000 series takes advantage of the bipolar structure: q q Peripheral cells surround the internal active chip area to interface with its external environment. Despite the row based architecture, "hard blocks" can be implemented with efficient floor planning organization. STKM2000 Cell libraries SGS-THOMSON Microelectronics introduces the "programmable" library; instead of working with a finite number of cells of the library, the designer has now access to an infinite number of functions. Defining only some properties, the designer is able to create himself the cells needed for his application. For example, the following electrical parameters are accessible and adjustable: q q q q q q q q very high speed NPN transistor : fT = 6 GHz very high speed vertical PNP : fT = 2.5 GHz This allows high gain - bandwith operational amplifier (50 MHz), low noise input amplifier, short propagation delay comparator, ... With the same BICMOS process, the analog CMOS performance come from the high density CMOS structure with a double poly layer for accurate capacitors, low consumption CMOS amplifier (30 A), CMOS switches, high accuracy switched capacitor filters (up to 100 kHz for center frequency). STKM2000 cell concepts SG S-T H O MSO N M ic ro el e ct r on i cs h as predesigned and precharacterized cells which are selected, placed and interconnected on the chip to implement digital and analog cells having different height and supply voltages. In addition some macrocells are designed as fixed blocks, so called "hard blocks" : filters, A/D and D/A converters; some hard blocks are automatically generated and parametrized from a compiler: S.C. filters, PLA, RAM, ROM... STKM2000 chip topology The chip is optimized versus the cell complexity, in a row based structure with different heights. gain-bandwith product phase margins, frequency compensation output buffer current biasing currents resistor, capacitor fields current, source or sink adjustable Ron switch resistor supply voltage assignment The analog library is operating in a large voltage range: 3V to 10V. The basic analog library contains: q q 60 analog CMOS functions 25 analog BIPOLAR functions From single transitor to 12 bits A to D converter (with autocalibration), each setup becomes possible. The digital CMOS library uses the same flexibility with a complete set of basic digital functions (NAND, NOR, Flip-Flop, ...) and some cell generators: q register, counter, logic comparator, ... More than 60 digital cells are available. 2/10 (R) STKM2000 SERIES Figure 2: The STKM2000 Series, a complete system solution ANALOG LIBRARY NPN transistor Lateral PNP Substrate PNP Isolated PNP NPN input comparator PNP input comparator N input comparator P input comparator N-MOS transistor P-MOS transistor NPN high-speed amplifier N input CMOS Op-Amp P input CMOS Op-Amp Crystal oscillator RC oscillator Transconductance Power-on reset (with adjustable threshold and hysteresis) Analog multiplexer Voltage to current converter Voltage reference 8 bits, A/D and D/A converters 12 bits A/D and D/A converters DIGITAL LIBRARY AND, NAND, OR, NOR, inverter Exclusive OR, NOR D latch Input buffer (TTL/CMOS) Output buffer (TTL/CMOS) Shift register Binary counter Decimal counter Magnitude comparator 3/10 (R) STKM2000 SERIES CAD SUPPORT: A.D.S. (Analog Design System) SGS-THOMSON Microelectronics has introduced a sophisticated CAD approach to reduce the development leadtime and to increase design flexibility and safety. Programmable cells in the library are defined as: q alternative cell or, q adjustable cell or, q telescopic cell or, q parametrisable cell Some specific parts of the design are automatically handled by an analog design manager, in order to: q q q q A major step has been made with the introduction of function generator and compiler approaches to improve design automation and design efficiency. Operational amplifier generator From a generic symbol and some properties, several parameters of the amplifier will be adjusted: q q reduce capture errors make unexperienced designer's task easier improve schematics lisibility check electrical design rules (Analog or Digital) q q Biasing current which controls major parameters of amplifier (gain-bandwidth, slew rate, power consumption). Frequency compensation which allows to adjust and optimize the dynamic parameters versus the capacitive and resistive load. Power down capabilities. Supply voltage of the cell. The Analog Design manager takes into account: q transconductance block generation q automatic cell biasing q unconnected pins and power down processing q multipower supplies processing Figure 3: Analog Design System (A.D.S.) flow A specific software manages all these properties and automatically updates all libraries included in the design flow: macro models and transistor level models, footprint, GDS2 layout, LVS netlist. Schematic Capture Digital Analog Symbols D DIGITAL Generator Data Base Filter Compiler G Netlist Extractor Analog Generator G Top Level Simulation SABER Behavioral Models G Programmable Cells Generation Digital Models D Transistor Models G Place & Route Cells Boxes G Analog Simulation ST SPICE Digital Simulation HILO 3 Back Annotation GDSII File Cells Layout G DRC/LVS PG Tape 4/10 (R) STKM2000 SERIES Filter compiler From the template defined at the beginning up to the complete layout, the software handles automatically the filter synthesis and the layout compilation: q evaluation/mathematical analysis q switched capacitor synthesis q simulation q Monte-Carlo analysis q layout generation Any kind of filters is available from 2nd up to 12th order. Digital cell generator For a set of basic digital cells, the user has access to generators which handle the netlists and interface with the layout tools. The schematic capture uses a block which is programma ble according t o t he required complexity. The generator creates a " so-called" soft macrocell taking into account the complete netlist: q q q counters shift registers magnitude comparators, ... A part from the software automation, the A.D.S. CAD tool works around standard softwares. The CAD approach is compatible with both approaches: q q VAXTM/VMS operating system SUNTM/UNIX operating system SUNTM EDGE (CADENCETM) MOZART (SGS-THOMSON) ST-SPICE (SGS-THOMSON) SABER (ANALOGYTM) VAXTM Schematic capture CASS (SILVAR LISCOTM) Logic simulation HILO 3 (GENRADTM) Analog simulation ST-SPICE (SGS-THOMSON) Top level simulation SABER (ANALOGYTM) Layout CALMP (SILVAR LISCOTM) DRC - LVS DRACULA (CADENCETM) EDGE (CADENCETM) EDGE (CADENCETM) 5/10 (R) STKM2000 SERIES Customer design interface SGS-THOMSON Micorelectronics has developed several interfaces for customers giving them easy and flexible design approaches for STKM2000. Users can access Analog Design System (A.D.S.): q q q q q q Dazix System Mentor Graphics Sun In that case,direct interfaces will be offered in order to make design implementation with A.D.S. (layout and test generations). According to these design possibilities, SGS- THOMSON defines 3 main interfaces. Figure 4 outlines these interfaces. Each interface details the responsibilities of customer and SGS-THOMSON during circuit development flow. via SGS-THOMSON design centers via SGS-THOMSON associated design centers via CAE workstations C AE w o rst at i o n ca p ab i l it i e s a re und er development on: Figure 4: SGS-THOMSON - CUSTOMER interfaces Interface 2 Responsibility level Circuit definition Schematics Simulations Layout Final control Prototyping phase ST + Ctm Breadboard schematics Ctm Interface 3 Simulated schematics Interface 4 Layout tape Ctm Ctm ST ST ST + Ctm ST + Ctm ST ST ST 6/10 (R) STKM2000 SERIES MAXIMUM RATINGS Symbol VDD VI, VO II, IO Tstg Parameter Supply voltage I/O voltage I/O current storage temp. (ceramic) storage temp. (plastic) Min - 0.5 - 0.5 - 40 - 65 - 40 Max 12.0 VDD + 0.5 + 40 + 150 + 125 Unit V V nA o o C C Note 1: Stresses above those under "maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation for the device at these or any other RECOMMENDED DC OPERATING CONDITIONS Voltage referred to VSS Symbol VDD Tamb Parameter Operating supply voltage Operating ambient temperature Military Industrial Commercial conditions above indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Min 2.7 Max 11 Unit V - 55 - 40 0 + 125 + 85 + 70 o o o C C C DIGITAL LIBRARY AC ELECTRICAL CHARACTERISTICS ABSTRACT Standard condition = 2 loads + 1 mm of metal interconnect Cell code IV1 ND2 NR2 FD1 Description Standard inverter 2 - input NAND 2 - input NOR D Flip - Flop From C to QN TSU TH TWH TWL OB11 CMOS inverting output buffer capacitance load = 100 pF 12.4 12.3 ns 6.44 8.26 5.00 1.75 8.25 5.00 ns VDD = 10V 10%, T = 25oC TPHL 2.26 1.74 2.55 TPLH 2.01 2.44 2.02 OTHER ns ns ns Unit 7/10 (R) STKM2000 SERIES DC GENERAL ELECTRICAL CHARACTERISTICS VDD = 5V 10% or VDD = 10V 10% (unless otherwise specified) Symbol VIH Parameter High level TTL input voltage Condition VDD = 5V 10% To = 0oC / + 70oC To = - 40oC / + 85oC To = - 55oC / + 125oC VIL VIH VIL IOZH Low level TTL input voltage High level CMOS input voltage Low level CMOS input voltage Tristate output leakage current VO = VDD To = 0oC / + 70oC To = - 40oC / + 85oC To = - 55oC / + 125oC IOZL VO = VSS To = 0oC / + 70oC To = - 40oC / + 85oC To = - 55oC / + 125oC IIH High level input leakage current VO = VDD To = 0oC / + 70oC T = - 40 C / + 85 C To = - 55oC / + 125oC IIL Low level input leakage current VI = VSS To = 0oC / + 70oC To = - 40oC / + 85oC To = - 55oC / + 125oC ICC Max admissible current per pin: - analog - digital 20 40 mA mA - 1.0 - 3.0 - 5.0 A A A o o o Min 2.0 2.25 2.25 Typ Max Unit V V V VDD = 5V 10% all temp. ranges 70%VDD 0.8 V V V 30%VDD 2.5 5 10 - 2.5 - 5.0 - 10.0 1.0 3.0 5.0 V A A A A A A A A A A 8/10 (R) STKM2000 SERIES ANALOG LIBRARY AC ELECTRICAL CHARACTERISTICS ABSTRACT Cell code CMP11 Description Static CMOS comparator CMP31 Static BICMOS comparator CPX11 Capacitor fields Parameters Test conditions Propagation delay (overdrive = 5 mV) Offset Propagation delay (overdrive = 5 mV) Offset Unit capacitance Capacitor value range Absolute accuracy Matching (capacitor ratio) CPP11 RPM/PPM Monolithic Capacitor Resistor/Potentiometer P-Base Capacitor range Absolute accuracy Resistor value range Absolute accuracy Matching Temperature coefficient Voltage coefficient SWI1 MN11 OPA31 Analog switch Telescopic NMOS transistor General purpose MOS Operational amplifier Unity gain bandwidth Current consumption Phase margin (C1 = 100 pF, R2 = 10 k) Offset OPA41 Internal bipolar Operational Amplifier Unity gain-bandwidth current consumption Phase margin (CL = 15 pF, RL = 100k) Offset OPA71 Rail to rail external MOS operational Amplifier Unity gain bandwidth current consumption Phase margin (CL = 100 pF, RL = 100K) Offset OTA11 MOS transconductance amplifier POR11 VRF11 Programmable Power on Reset Voltage bandgap reference Active Level Accuracy Hysteresis Accuracy Output voltage accuracy Temperature coefficient Current consumption 15 5 5 2 100 % % % ppm A 9/10 (R) Min Typ 1 3 90 2 0.1 Max 1.4 10 110 7 50 15 Unit ms mV ns mV pF pF % % pF % K % % % % K 0.1 0.5 1 6.5 1.0 100 15 3000 20 1 0.2 0.05 Elementary switch RON value Number of switches in parallel RON value 1 5 100 3.3 700 60 3 9 240 62 1 2.3 360 80 3 24 25 3 4.6 MHz A o 10 30 mV MHz A o 5 mV MHz uA o 10 mV MHz Unity gain - bandwidth (CL = 2 pF) STKM2000 SERIES ANALOG LIBRARY AC ELECTRICAL CHARACTERISTICS ABSTRACT Cell code OSC11 OSC41P Description Programmable crystal oscillator RC oscillator Frequency Stability versus temperature Stability versus voltage OSC31P One pad I.C oscillator Frequency Stability versus temperature Stability versus voltage Filters ADC81 8 bit analog to digital converter DAC81 8 bit analog to digital converter Order Center frequency Conversion time Integral non linearity Differential non linearity Conversion time (CL = 2 pF) Integral non linearity 0.5 LSB 2 2 0.01 0.5 12 100 5 0.5 0.5 1 KHz s LSB LSB s 1 100 0.01 0.5 200 800 KHz % / oC %/V KHz % / oC %/V Parameters Test conditions Frequency 0.1 20 MHz Min Typ Max Unit Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All rights reserved. Purchase of I 2C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I 2C Patent. Rights to use these com2 ponents in an I C system is granted provided that the system conforms to the I 2C Standard Specification as defined by Philips. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 10/10 (R) |
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